FIG. 1 is a diagram of a memory array for a conventional NOR type semiconductor memory device. FIG. 2 is a timing diagram of a data reading operation for the memory device shown in FIG. 1. The memory device shown in FIG. 1 refers particularly to a mask read only memory (hereinafter referred to as a "mask ROM") having a plurality of NOR type memory cells. The hierarchical bit line system of the array having NOR structured memory cells is described in detail in a paper entitled "16 Mb ROM Design Using Bank Select Architecture," pp. 85-86, Digest of Technical Papers, VLSI Circuit Symposium held in Tokyo, Japan, August 1988, incorporated herein by reference.
Referring to FIG. 2, the data reading operation of the NOR type mask ROM shown in FIG. 1 is divided into three periods: a bit line precharge period 1, a data sense period 2, and a data output period 3. During the bit line precharge period 1, all main bit lines MBL0 to MBLi are precharged to a precharge voltage Vpre (e.g., 1 V to 2 V) to read the data stored in an addressed memory cell. The data sense period 2 begins when the main bit lines are precharged and the precharge operation ends. During the data sense period 2, the NOR device detects whether the addressed memory cell is an on-cell or an off-cell. Namely, the NOR device senses a voltage level on a main bit line associated with the addressed memory cell. During the data output period 3, the data sensed during the data sense period 2 is provided to external circuitry.
The data reading operation will be described in detail with reference to FIG. 2. Assume a j-th block of a plurality of array blocks 110 within memory cell 100 is selected. The subscript j indicates a j-th array block but does not indicate a plurality of signs. During the precharge period 1 of the data reading operation, ground potential (i.e., 0 V) is applied to word lines WL0 to WLm and even-numbered and odd-numbered bank selection signals SEj and SOj, respectively, and a precharge voltage Vpre is applied to the main bit lines MBL0 to MBLi where i is an integer. During the data sense period 2, the voltage level of the even-numbered bank selecting signal SEj and the voltage level of an addressed or selected word line WL0 increases from the ground potential to a power supply voltage VCC.
As shown in FIG. 2, the data stored in a memory cell corresponding to the selected word line WL0 and a selected main bit line MBL1 is detected by a sense amplifier circuit SA. If the addressed memory cell is an on-cell, the selected main bit line has a voltage level lower than the precharge voltage Vpre because of the current flowing through the current path thereof (the on-cell operates as a current sink). On the other hand, if the addressed memory cell is an off-cell, the voltage level of the selected main bit line MBL1 is maintained at the precharge voltage Vpre. Then, the sense amplifier circuit SA senses the voltage level on the selected main bit line MBL1 and provides the data sensed to external circuitry during output period 3.
Suppose that a memory cell M00 associated with the word line WL0, the main bit line MBL1, and the even-numbered bank selection signal SEj are selected and read using the above-mentioned data reading method. Suppose also that the selected memory cell M00 is an off-cell and that the memory cells M01, M02, M03, and M04 are commonly connected to the selected word line WL0, adjacent to the cell M00 and are on-cells. Under these conditions, during the data sense period 2, the voltage Vpre applied to the selected main bit line MBL1 during the precharge period 1 is discharged into an adjacent main bit line MBL2 via the memory cells M01 and M02 connected to the same word line WL0. As a result, the sensing margin and the reading speed for the selected memory cell M00 (e.g., the off-cell) drops off.